Low-Power Design for Test Techniques in Sub-7nm Technologies

Abstract

Low-power Design for Test (DFT) techniques have become essential in the advancement of sub-7nm semiconductor technologies. As transistor densities increase and physical dimensions decrease, the challenges of managing power consumption during testing have grown significantly. This article explores critical methods for minimizing power consumption while maintaining comprehensive fault coverage in advanced technology nodes. The convergence of increased design complexity and the imperative to reduce power consumption during testing has spurred the development of specialized approaches including switching activity reduction, strategic clock gating, test partitioning, and adaptive testing techniques. These innovations address the unique challenges posed by sub-7nm technologies while ensuring manufacturability and reliability throughout the testing process.