Joint Optimization of Sequential Elements and Metal Layer Usage for Advanced Semiconductor Physical Design Using Artificial Intelligence and Machine Learning

Abstract

Technology nodes below 2nm pose a whole new set of challenges, primarily concerning power, performance, area (PPA) optimization, and routing complexity. Sequential elements such as flip-flops and latches are the leading contributors to dynamic power consumption and are among the major timing bottlenecks, while dense metal stacks cause resistance and congestion issues that limit manufacturability. This work presents a unified machine learning framework that enables optimum sequential elements use and metal layer assignment with a design automation process. The framework uses graph neural networks (GNN) to learn the topological patterns of netlist structures for property extraction and applies reinforcement learning agents to make instantaneous decisions for real-time metal allocation over voltage/clocks, routing congestion maps, IR drop limitations, and timing criticality weights. For high-dimensional embeddings of raw feature data, simulation traces, toggle patterns ,and physical layout characteristics are converted to a graph node structure through feature engineering techniques and utilized for semantic clustering. The joint cost function mitigates timing degradation, IR drop penalties, register count, and routing congestion. Adaptive weights allow for distinct tuning for joins and improve usability. Showing implementations in TSMC N2 technology means that there were significant improvements in the following: flip-flop reductions, setup violations severity, improved routing congestion, overall design robustness, and complete management of metal layer assignments. The framework works with existing EDA tool chains through further TCL scripting or Python APIs without altering functional correctness or other manufacturing alteration elements.